Crossbar

A crossbar is a type of processor interconnect. You will learn about a number of different interconnects later in the course when you treat multi-core systems and memory coherence between them, but suffice to say that the crossbar interconnect is a somewhat simple mechanism, providing an all-to-all connection using a series of $n$ muxes for $n^2$ connections [Bauer p. 267].

Creating the Crossbar

Once again, gem5 has a SimObject we can derive our design from. So once again, we create our separate crossbars.py file and import the coherent crossbar:

from m5.objects import CoherentXBar

Now we can define the class of our crossbar:

class MyXBar(CoherentXBar):
    # The width is the number of bits we can transmit at once
    width = 256

    # Some other neat latency settings
    frontend_latency = 5
    forward_latency = 3
    response_latency = 5
    # You'll learn more about snooping with multiprocessors
    snoop_response_latency = 3

    # Is this where multiple caches combine into a shared cache?
    point_of_unification = True

note

You can find the information about all of the fields in the file $GEM_SRC/mem/coherent_xbar.{cc hh py} if you're curious.

Code so far

interconnect.py

# Import the connections from m5
from m5.objects import CoherentXBar

class MyXBar(CoherentXBar):
    # The width is the number of bits we can transmit at once
    width = 256

    # Some other neat latency settings
    frontend_latency = 5
    forward_latency = 3
    response_latency = 5
    # You'll learn more about snooping with multiprocessors
    snoop_response_latency = 3

    # Is this where multiple caches combine into a shared cache?
    point_of_unification = True